On June 25, 2026, IBM announced what it calls the world’s first sub-1-nanometer-node chip technology. The headline needs unpacking. The “0.7 nanometer” label is a technology-generation designation, not a claim that every critical physical feature on the device measures 0.7 nanometers. The important development is architectural: IBM’s NanoStack approach sequentially integrates complementary metal-oxide-semiconductor transistors in vertically stacked nanosheet layers.
IBM says the demonstration can place nearly 100 billion transistors on a fingernail-size chip, roughly doubling the density of its 2021 2-nanometer demonstration. The underlying research is more cautious than the press release. A 2025 VLSI Technology and Circuits paper reports a manufacturable sequential integration flow and projects, for a four-track NanoStack cell, about 50 percent area scaling, about 50 percent higher performance at the same power, or about 70 percent lower power at the same performance, relative to the 2-nanometer node. Those are architecture-level projections, not measured results from a mass-produced commercial processor.
That distinction matters. IBM has demonstrated key building blocks, including stacked nanosheet devices, thin dielectric bonding, and functional inverter operation. It has not shown that a full commercial product using the architecture can be manufactured at high yield, qualified for long service, and produced at competitive cost. IBM says it sees a path to production as early as five years from the announcement. The proper conclusion is neither dismissal nor triumph: NanoStack is a credible research milestone with significant commercialization work still ahead.
Moore’s Law Was Never Only About Dimensions
The announcement is useful because it clarifies what semiconductor progress has become. Gordon Moore’s 1965 observation linked component density to economics. He noted that, over the period he examined, manufacturers had been able to place more components on integrated circuits while reducing cost per component. The industry later turned that observation into a roadmap for repeated gains in density, performance, and cost.
For decades, geometric shrinkage carried much of that burden. It no longer carries it alone. The industry now pursues gains across device structure, materials, lithography, memory architecture, power delivery, packaging, and system design. High-bandwidth memory stacks memory dies. Chiplets divide large designs into smaller dies connected in a package. Backside power-delivery schemes separate some power routing from signal routing. Optical links are moving closer to compute to address the growing energy and bandwidth cost of moving data. Specialized accelerators exchange some general-purpose flexibility for higher performance and efficiency on selected workloads.
NanoStack belongs in that broader transition. The semiconductor roadmap is becoming three-dimensional and system-level. Progress increasingly depends on the co-design of transistors, memory, interconnects, packaging, power delivery, cooling, and software. The transistor remains fundamental, but it is no longer the only place where the cost curve is fought.
Efficiency Does Not Set Total Demand
That shift has a direct implication for the AI-energy debate: a more efficient chip can reduce electricity use for a fixed computation, but it does not determine how much computation the market will buy.
The International Energy Agency’s 2025 Energy and AI analysis models precisely this uncertainty. Its base case projects global data-center electricity consumption rising from about 415 terawatt-hours in 2024 to about 945 terawatt-hours in 2030. Its high-efficiency case assumes faster gains in hardware, software, and infrastructure and produces materially lower consumption than the base case for the same level of digital-service demand. Its higher-adoption case produces much greater demand. Efficiency matters, but adoption and deployment matter too.
This is where the rebound argument is useful—if stated carefully. William Stanley Jevons argued in 1865 that more efficient steam engines could expand rather than contract coal use by making coal-powered work cheaper and more attractive. Modern research treats rebound as a family of mechanisms whose size varies by technology, market, time horizon, and demand elasticity. Efficiency savings can be partly offset by additional use; “backfire,” in which total resource use rises because of the efficiency improvement itself, is not a universal law.
For AI, the relevant question is empirical: how responsive is demand for useful computation to falling cost? The answer is not yet known. But there are reasons to expect substantial demand response. Lower inference cost can make applications economical at higher frequency, lower latency, or larger scale. Better models can create new tasks rather than merely perform old tasks more efficiently. AI can be embedded in software development, search, logistics, scientific workflows, customer service, industrial controls, robotics, and other processes whose eventual usage is still uncertain.
The defensible claim is therefore conditional. Chip and model efficiency will reduce the energy required for a given amount of useful work. Total electricity consumption will rise or fall according to whether growth in useful work outruns those efficiency gains.
The Bottleneck Is Becoming a System
The IEA’s forecasts already incorporate major efficiency improvements and still show rapid electricity-demand growth in its base case. It also emphasizes a critical physical asymmetry: a large data center can be developed in roughly two to three years, while the power infrastructure needed to serve it can require longer planning and construction cycles.
That timing mismatch is turning AI infrastructure into a power-system problem. The constraint is not simply annual energy. Large computing campuses need capacity at specific locations, on specific timelines, with high reliability. Serving them can require generation, transmission, substations, transformers, distribution upgrades, internal power systems, backup systems, and cooling infrastructure. The difficulty is regional. The world can have adequate generation in aggregate while a particular site lacks deliverable capacity.
US evidence illustrates the scale of the uncertainty. Lawrence Berkeley National Laboratory’s June 2026 update estimates that data centers could account for 11.8 percent of US electricity consumption in 2030 in its reference case, with a compounded uncertainty range of 9.5 to 15.3 percent. The laboratory estimates 649 terawatt-hours in the reference case and a range of 521 to 843 terawatt-hours across its broad uncertainty scenarios. Those are modeled scenarios, not commitments or outcomes, but they show why utilities cannot plan from a single-point forecast.
The supply side has its own queues. Berkeley Lab reports that, at the end of 2025, more than 2,060 gigawatts of proposed generation and storage were actively seeking US transmission interconnection. The same dataset shows that most proposed capacity historically has not reached operation, while the projects that do succeed are taking longer to move from request to commercial operation. Generator queues are not the same thing as data-center load-interconnection queues, but they expose a related constraint: adding supply and network capacity is neither automatic nor fast.
Equipment can be a separate bottleneck. The US Department of Energy has documented long lead times and supply-chain risks for transformers and other grid components. The practical consequence is that a data-center developer can have capital, servers, and land and still wait on the electrical system that makes the site usable.
More Compute per Rack Can Raise Facility Intensity
Semiconductor efficiency also interacts with facility design in a way that simple “joules per operation” comparisons miss. More efficient computing can enable more computation within the same power envelope. It can also support denser configurations that concentrate more electrical load and heat in less floor area. The current generation of rack-scale AI systems makes the engineering direction visible. NVIDIA’s GB200 NVL72 architecture, for example, is designed around roughly 120 kilowatts of rack cooling capacity and direct liquid cooling. NVIDIA has also described future data-center power architectures intended to support racks from 100 kilowatts to more than 1 megawatt.
Vendor roadmaps are not neutral forecasts, and not every data center will approach those densities. But the engineering implication is straightforward: as compute density rises, power conversion, busways, cooling loops, pumps, heat rejection, redundancy design, and maintenance practices become central constraints. A better processor can reduce energy per task while making the surrounding facility more technically demanding.
This is one reason the phrase “AI electricity demand” can mislead. The issue is not one number. It is a coupled system: workload demand, accelerator supply, utilization, model efficiency, rack density, cooling architecture, utility service, local network capacity, generation availability, and construction time.
The Forecasting Problem Is Two-Sided
The draft version of the AI-energy story often asks one question: How efficient will the chips become?
The better framework asks at least two:
First, how fast will the energy required for a unit of useful AI service fall? That depends on chips, memory, networking, software, model architecture, quantization, sparsity, batching, utilization, and facility efficiency.
Second, how fast will demand for useful AI service grow as capability improves and cost falls? That depends on business value, product design, latency requirements, labor substitution and complementarity, regulation, customer adoption, and the emergence of new machine-intensive workflows.
Training and inference should also be separated. Training a large model is an episodic development workload. Inference is the repeated use of deployed models. The long-run balance between them is not fixed and varies by service. Public evidence does not justify a universal claim that inference will dominate every model’s lifetime energy use. It does justify the narrower point that inference can become a persistent, high-volume load whose importance rises with deployment scale.
The forecasting error to avoid is collapsing technical efficiency and demand growth into a single trend line. A forecast that improves efficiency without modeling adoption can overstate demand. A forecast that assumes fixed demand can overstate savings. Both sides of the equation are uncertain.
The Next Constraint Is Institutional as Well as Physical
The downstream bottleneck is not only engineering. It is also institutional. Large-load growth is forcing utilities, grid operators, state regulators, and federal regulators to revisit forecasting, interconnection, rate design, and cost allocation. Berkeley Lab’s review of large-load rate designs identifies recurring objectives: allocate system costs fairly, reduce the risk that other customers pay for stranded investments, manage resource-adequacy and operational risks, and provide service structures suited to customers with unusual scale and timing.
Federal policy is also moving, but it is not settled into one national rulebook. In December 2025, the Federal Energy Regulatory Commission directed PJM Interconnection to develop clearer tariff rules for large loads co-located with generation. In January 2026, FERC approved the Southwest Power Pool’s High Impact Large Load initiative. On June 18, 2026, FERC issued additional targeted actions and show-cause proceedings concerning large-load integration in several organized markets. These actions have different procedural postures and regional scopes; they should not be described as a single final national policy.
The underlying problem is real. Utilities must distinguish credible projects from speculative requests, decide what financial commitments are required before infrastructure is built, and determine how upgrade costs and stranded-asset risks are allocated. A project that requests hundreds of megawatts and then fails to materialize can distort planning. A project that arrives faster than forecast can create the opposite problem.
The quality of AI infrastructure policy will therefore depend on ordinary-sounding details: deposits, minimum-demand charges, contract terms, collateral, ramp schedules, cost-recovery agreements, curtailment provisions, and the evidentiary standards used in load forecasts. Those details will decide whether speed and fairness can coexist.
What the IBM Announcement Actually Means
IBM’s NanoStack work does not prove that Moore’s Law has been extended for another decade. It shows a plausible technical route for continued density and efficiency gains beyond conventional two-dimensional scaling.
For AI and energy, the significance is not that one architecture will determine electricity demand. It is that semiconductor progress can continue while the binding constraints move outward. Cheaper computation can reduce the electricity needed for a fixed service. It can also broaden the market for computation. Higher compute density can lower the floor space required for a workload while raising the electrical and thermal intensity of each rack. Faster deployment of servers can create value while colliding with slower cycles for grid planning, equipment manufacturing, permitting, and construction.
That is the stronger meaning of “Moore’s Law moving downstream.” The phrase should not be read literally: a transformer factory is not the new transistor fab, and grid expansion does not follow a semiconductor doubling law. The point is about constraint migration. As the industry finds new ways to push the compute frontier, more of the difficulty of scaling AI appears in the systems around the chip.
The next era of computing will still be decided in cleanrooms. But it will also be decided in substations, cooling plants, transformer factories, regulatory dockets, utility contracts, and transmission corridors.
The frontier has not left the chip. It has acquired a much larger perimeter.
Sources
International Business Machines Corp. (IBM), “IBM Debuts World’s First Sub-1 Nanometer Chip Technology,” June 25, 2026. https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology
S. Reboh et al., “NanoStack Transistor Architecture for CMOS 7A Node and Beyond,” VLSI Technology and Circuits 2025, June 8, 2025, doi:10.23919/VLSITechnologyandCir65189.2025.11074866. https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074866
Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics 38, no. 8 (April 19, 1965): 114–17. https://download.intel.com/newsroom/2023/manufacturing/moores-law-electronics.pdf
International Energy Agency, Energy and AI, 2025, especially “Energy Demand from AI.” https://www.iea.org/reports/energy-and-ai/energy-demand-from-ai
Steve Sorrell et al., “The Jevons Paradox Unravelled: A Multi-Level Typology of Rebound Effects and Mechanisms,” Energy Research & Social Science 74 (2021): 101982. https://doi.org/10.1016/j.erss.2021.101982
Kenneth Gillingham, David Rapson, and Gernot Wagner, “The Rebound Effect and Energy Efficiency Policy,” Review of Environmental Economics and Policy 10, no. 1 (2016): 68–88. https://doi.org/10.1093/reep/rev017
Sarah Josephine Smith et al., United States Data Center Energy Usage Report: 2025 Update, Lawrence Berkeley National Laboratory, June 2026. https://eta.lbl.gov/publications/united-states-data-center-energy-2025
Joseph Rand et al., “Queued Up: 2026 Edition, Characteristics of Power Plants Seeking Transmission Interconnection as of the End of 2025,” Lawrence Berkeley National Laboratory, 2026. https://emp.lbl.gov/queues
US Department of Energy, Office of Electricity, “Distribution Transformer Webinar Text Alternative,” June 30, 2026. https://www.energy.gov/oe/distribution-transformer-webinar-text-alternative
NVIDIA, “NVIDIA Contributes NVIDIA GB200 NVL72 Designs to Open Compute Project,” October 15, 2024. https://developer.nvidia.com/blog/nvidia-contributes-nvidia-gb200-nvl72-designs-to-open-compute-project/
NVIDIA, “NVIDIA 800 VDC Architecture Will Power the Next Generation of AI Factories,” May 20, 2025. https://developer.nvidia.com/blog/nvidia-800-v-hvdc-architecture-will-power-the-next-generation-of-ai-factories/
Andrew Satchwell et al., “Electricity Rate Designs for Large Loads: Evolving Practices and Opportunities,” Lawrence Berkeley National Laboratory, January 2025. https://emp.lbl.gov/publications/electricity-rate-designs-large-loads
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Federal Energy Regulatory Commission, “FERC Launches Aggressive Targeted Action to Speed Large Load Integration,” June 18, 2026. https://www.ferc.gov/news-events/news/ferc-launches-aggressive-targeted-action-speed-large-load-integration
